1. Field of the Invention
The present invention generally relates a memory cell and, more particularly, is related to an apparatus and method using advanced capacitor dielectrics in the construction of a random access memory (RAM) memory cell.
2. Description of Related Art
As is well known in the art, there are basically two types of metal oxide semiconductor (MOS) random access memories (RAMS): static and dynamic. A static RAM or SRAM is a form of semiconductor memory based on the logic circuit known as a flip-flop, which retains information as long as there is enough power to operate the device. These flip-flops have to be simple in order to minimize the silicon area per cell, which is very important since the cell array constitutes by far the largest part of the memory chip. One problem with standard SRAMs is their large size, owing to the use of six transistors in each memory cell where all six are aligned in one plane of the silicon wafer containing them.
Dynamic RAMs (DRAMs) on the other hand store binary data on capacitors resulting in a further reduction in cell area at the expense of more elaborate read/write circuitry. The binary data stored in DRAMs is in the form of the charge on the capacitor. Due to various leakage effects (i.e. current drain) that are inevitably present, the capacitor charge will eventually leak off. Thus, to ensure proper operation of DRAMs, a refresh operation must be completed periodically.
During the refresh operation, the DRAM memory cells' content is read and the data stored therein is rewritten, thus restoring the capacitor charge to its proper value. The refresh operation must be performed every few milliseconds (e.g. eight to sixteen milliseconds) and thus implies the necessity of having a clock connection to the DRAM circuit. This periodic refresh operation required in the DRAMs operation requires that additional refresh circuitry be included in the design, thereby increasing the surface area of the circuit.
Regardless of the refresh operation, DRAMs are preferred over SRAMs. This is because the DRAM memory cell has significantly fewer components and as a result, the DRAMs achieve greater packing density than is possible with any static RAM. Despite being slower, DRAMs are more commonly used than SRAMs because of the smaller DRAM cell design that allows a DRAM to hold up to four times as much data as a SRAM within the same surface area on the integrated circuit.
However, there have been problems in the past constructing capacitors on integrated circuits for usage in a RAM. Discrete capacitors using high dielectric constant films of Silicon (Si) and Silicon Oxide (SiO.sub.2) have been studied since the 1950s. Nevertheless, incompatibilities with the Si--SiO.sub.2 technology progression have inhibited these dielectrics from being used in an integrated circuit manufacturing environment.
Several attempts have been made to merge high dielectric discrete capacitors and DRAM technologies in a brute force manner by either inserting existing access-transistor and stacked-capacitor fabrication modules below the first level metal interconnect of their Application Specific Integrated Circuit (ASIC) technology or by burying a trench-capacitor underneath an access-transistor.
The first approach leads to a technology that has a high mask count, and is somewhat problematic because of the introduction of additional thermal cycles to the fabrication process and the increased aspect ratio of the contact window etch in the first level metal interconnect intended for the ASIC transistors.
The trench-capacitor approach is more reasonable from a processing point of view, however, it is not considered scalable. This scalability problem is due to difficulty associated with depositing advanced dielectrics in a deep trench.
Heretofore, manufactures have been unable to fulfill the aspiration of providing a RAM memory cell with temperature insensitivity and a high speed of access along with reduced circuit complexity and size.